|CPU||Quad-Core ARM Cortex-A53|
|Memory||up to 3 GB DDR3 / DDR3L, 32-bit bus|
|Video||HDMI 1.4 with HDCP 1.2, TV CVBS|
|Audio||I2S, PCM, AC97|
|Network||GBit MAC, integrated 10/100M PHY|
|Storage||NAND, SPI NOR, MMC|
|USB||1x OTG, 3x Host, all with integrated PHY|
|Other||FBGA347, 14 mm x 14 mm, 0.65 mm Pitch|
|Release Date||May 2016|
Allwinner H5 (sun50i) SoC features a Quad-Core Cortex-A53 ARM CPU, and a Mali450 MP4 GPU from ARM.
The H5 is basically an Allwinner H3 with the Cortex-A7 cores replaced with Cortex-A53 cores (ARM64 architecture). They share most of the memory map, clocks, interrupts and also use the same IP blocks. Differences between the H3 and the H5 seem to be:
- The MMC controller has been updated to support faster transfer modes (HS-400). The MMC clocks have changed on the way, now the MMC controller itself provides support for the output and sample phase. So the MMC controller seems to be closer to the A64.
- The H3 has SRAM A1 mapped at address 0, the BROM is at 0xffff0000. The H5 (much like the A64) has its BROM mapped at address 0, SRAM A1 is mapped right behind it at 0x10000 (64KB).
- From comparing the datasheets the pinout seems to be backwards compatible to the H3 (so an H5 can be placed into a H3 PCB layout). The differences found are:
- Pins H8, M5 and T9 are labelled "GND_TV", "HGND" and "GND_CPUFB" on the H3, respectively, but just labelled as generic "GND" pins on the H5. This may just be a naming change.
- Pin G15 supplies VCC_IO voltage to PortA on the H3 (together with other pins), while it's dedicated to PortC on the H5. This allows to drive the MMC2 with a different voltage (1.8V), to take advantage of the faster HS-400 transfer mode.
- Pin J12 is one of the "VDD_SYS" pins on the H3, while it's singled out as "VDD_GPUFB" on the H5. There is no pin for "VDD_GPUFB" on the H3.
- Pin T10 is labelled "VDD_CPUFB" on the H3, but there is neither such a pin nor such a label on the H5.
The fact that the H5 uses the (SRAM and BROM) memory map of the A64, but the pinmuxing of the H3 makes it incompatible to both of the chips, especially for bootstrap code (boot0, SPL).
H5 SoC Features
- ARM Cortex-A53 Quad-Core (r0p4, revidr=0x180) (scroll down for the PDF link)
- 512KiB L2-Cache
- 32KiB (Instruction) / 32KiB (Data) L1-Cache per core
- SIMD NEON (including double-precision floating point), VFP4
- Cryptography Extension (SHA and AES instructions)
- Unlike the Cortex-A53 in A64, it is not affected by any critical CatA errata.
- ARM Mali450 MP4
- Featuring 2 vertex shader (GP) and 4 fragment shaders (PP).
- Complies with OpenGL ES 2.0
- DDR3/DDR3L controller (up to 3GB of 667MHz(DDR-1333))
- NAND Flash controller and 64-bit ECC
- File:Allwinner H5 Datasheet V1.0.pdf - H5 Datasheet v1.0 (really just a marketing blurb), 20 may 2016, 3MB, 68 pages
- File:Allwinner H5 Manual v1.0.pdf - H5 Datasheet v1.0, 20 may 2016, recompressed 6MB, 705 pages
- H5 User Manual - original file of the above, 23.7MB, 705 pages
- Some 'confidental' documentation in Chinese
H5 SoC is supported since v2017.05. See the device specific pages for defconfigs.
Linux 4.12 added initial support for the H5 SoC. Features such as ethernet still require official kernel 4.13+ or manual patching.
Boots an arm64 Linux 4.8 build with a minimal change to allow selecting the H3 pinctrl driver on arm64. Also one has to manually select CONFIG_SUN8I_H3_CCU by enabling:
Device Drivers -> Common Clock Framework -> Clock support for Allwinner SoCs -> Support for the Allwinner H3 CCU
MMC support requires some patches or a 4.9 kernel.